1. Field of the Invention
The invention relates in general to systems for generating layouts for integrated circuit devices and in particular to a layout system having a graphical user interface enabling a user to create and modify passive devices within an IC layout.
2. Description of Related Art
A typical integrated circuit includes a semiconductor substrate doped in a desired pattern and several layers of insulating and conductive material sequentially formed above the substrate, each layer having a particular pattern of filled and empty areas. The doping patterns in the substrate and the layer patterns define structures of IC devices such as gates, transistors and passive devices (inductors, capacitors and resistors), along with the conductive networks (“nets”) that interconnect the IC devices.
An IC designer typically produces an IC design in the form of a hardware description language (HDL) netlist, a computer file describing the IC at a relatively high level of abstraction, for example using Boolean expressions to describe IC logic. The designer then uses a syntheses tool to convert the HDL level netlist into a gate level netlist describing the IC as being formed by a set of interconnected instances of cells described by a cell library. Each cell is an IC component, such as for example a transistor, a gate or a higher-level component such as a memory, arithmetic logic unit, or central processing unit. The cell library includes an entry for each cell describing the internal layout of the cell including the substrate doping pattern and the layer patterns above the substrate needed to form the cell. After creating the gate level netlist, the designer employs computer-aided placement and routing (P&R) tools to generate an IC layout indicating the position of each cell instance with the layout and the routing of the nets between the cell instance terminals. The cell library provides the data defining the internal layout of each cell instance.
An IC designer normally does not have to directly specify the IC's doping and layer patterns except in cases where the IC is to include a component not described in a cell library. In such cases the IC designer can use a graphics program to draw the pattern for each layer forming the component. Designers often create passive devices such as resistors, capacitors and inductors this way. For example, as illustrated in FIG. 1 a resistor 10 can be nothing more than a rectangular section of a layer of resistive material 11 such as polysilicon with contacts 12 linking opposite ends of that rectangular section through vias 14 to nets formed on conductive layers above. The resistance of resistor 10 is a function of the length, width, thickness and resistivity of the material between its contacts 12. Although the thickness and resistivity of material 11 are fixed, an IC designer can control the resistance of the resistor by choosing its length and width. A designer can also modify the shape of a resistor as necessary to make it fit in some confined area of the layout. For example FIG. 2 shows a U-shaped resistor 16 that can have the same resistance as the straight resistor 10 of FIG. 1. An IC designer can form a capacitor from adjacent areas of two conductive layers separated by a dielectric layer, with the capacitance being a function of the shape and area of the conductive layers, and of the thickness and dielectric constant of the dielectric layer. A designer can form an inductor, for example, as a spiral of conductive material formed in one or more conductive layers of an IC.
Manually generating a layout for a passive component can be tedious and time-consuming, but automated layout systems allow a designer to write a macro procedure that can generate a passive device layout automatically. As illustrated in FIG. 3, a designer typically supplies various parameters defining characteristics of a passive device to the user-written macro procedures 20 on a graphical user interface (GUI) form 22, and the macro procedure then generates the passive device layout 24. For example, as illustrated in FIG. 4, data provided from the designer via a GUI form 26 specifies the resistor width (4.0 microns), the resistor value (200 Ohms) and the number (4) of resistor segments. When the designer presses the “Create” button 27, the macro procedure will generate an appropriately sized, 4-segment resistor 28.
Referring to FIG. 5, if the designer thereafter wishes to convert the 4-segment resistor 28 into a 2-segment resistor, the designer first selects resistor 28 in the layout so that the system will display GUI form 26 indicating its values. The designer then uses the form to alter the resistor value and number of segments, and the macro procedure then redraws the resistor as a two-segment resistor 29.
Since a passive device such as a resistor, capacitor or inductor can be of any of an infinite variety of shapes, they can be manually designed to fit into a wide variety of available spaces within an IC layout. But one difficulty with the prior art approach to automatically generate passive device layouts is that it requires the designer co write a separate macro procedure for each kind of shape. For example one, two, and four segment resistors require different macro procedures, though the procedures may allow for variation in dimensions. If the designer wants the layout tool to automatically generate a resistor having some shape for which a procedure is not available, the designer must create a new macro procedure for doing so, and that can be more time consuming that manually laying out the device. Thus it is often impractical for a designer to use automated procedures for creating passive device layouts when the space available for the passive device within an IC requires it to be of an unusual shape.
Various prior patents discuss method for automatically generating layouts for active device cells such as, for example, transistors and gates. U.S. Pat. No. 5,394,338 issued Feb. 28, 1995 to Shinohara et al describes a method of generating cell layouts for an IC based on models of the cells in which various dimensions of the cell are controlled by adjustable parameters.
U.S. Pat. No. 6,321,367 issued Nov. 20, 2001 describes a method for automatically generating a custom device layout including a step of specifying a device type and an associated set of device parameters. The device type is then matched to a selected cell in a cell library. Physical layout regions of the selected cell are then selectively modified in accordance with the device parameters. The physical layout regions may also be selectively modified in accordance with technology design rules in a design rule library. The physical layout regions of the selected cell are then drawn.
U.S. Pat. No. 6,457,163, issued Sep. 24, 2002 to Yang et al describes a method for generating an manipulating an IC layout for a multiple-gate semiconductor device, wherein the layout is comprised of a plurality of gate glue-blocks interconnected by a plurality of active-layer glue-blocks, working shapes of the gate glue-blocks are initially created according to user-defined gate glue-block parameters. Thereafter, working shapes of the active-layer glue-blocks are created in accordance with the working shapes of adjacent ones of the gate glue-blocks, in which the distances among the working shapes exceed minimum geometrical distances as defined by relevant design rules of an applied fabrication technology.
U.S. Pat. No. 6,804,809 issued Oct. 12, 2004 to West et al describes a method for creating a layout of a semiconductor device including first providing a plurality of partial-area layout cells and then generating the layout of the semiconductor device by placing the plurality of the partial-area layout cells together. The layout can be conveniently expanded to a desirable size by replicating or repeating certain repeatable cells.
What is needed is an IC layout system that can automatically generate passive devices layouts of a wide variety of shapes and other characteristics based on user input and which allows the user to easily adjust the layouts so that they fit within a variety of available spaces within an IC layout.